High-Performance Switch/Router Design:
Theory and Practice

The rapid evolution of high-speed switches, routers, and cross-connects over the past few years has lead to several advances in the theory and practice of high-performance switch architectures. With the rapid convergence of packet and circuit-switched services, it is crucial for designers and systems engineers to grasp and appreciate this evolution and new design paradigms. Whether it is lookups and packet classification or software design in the control plane, a number of new best practices have shaped how modern systems are architected.

Understanding the major developments of the last decade in this field, and having insights into future trends is crucial for building advanced software, chips, systems, and networks.

 

With this goal, this workshop covers:

• Switch architectures & fabrics: features, properties, applicability, practical realizations
• Analysis of data path processing: through a router, cross-connect, hybrid packet/TDM switch
• Comparative evaluation: Cisco Catalyst 6K family (large enterprise) versus the Juniper M40/160 (metro/core) and Gibson T640 (core); discussion of the key architectural aspects of edge/metro boxes, such as Unisphere/Juniper's ERX and Foundry's BigIron family.
• Forwarding, lookups, packet classification: methods, hardware realizations, and performance issues
• Scheduler design: theoretical limits, practical algorithms and implementations
• Output scheduling: fair queueing algorithms, practical considerations, QoS guarantees
• Considerations in modern router design: high-availability architectures, scalability, building services
• Techniques for building very high-capacity switches (time permitting): parallelism, optical fabrics (putting optics inside of routers)

A unique aspect of the workshop is that the exposition of the material is modulated based on the business and technial interests of the organization it is deliverd at. Thus, delivery at a software or systems company may involve greater emphasis and discussion (as required by the company or attendee questions) of software and/or algorithmic aspects, while delivery at a chip or components company may involve greater emphasis on hardware implementation complexities.

Audience: The workshop is targeted at system and network architects, advanced software or hardware development, system engineers, strategic marketing, management and application engineers.

Category: Intermediate to Advanced

Expected background: This is a second-level workshop that assumes that the audience is conversant with concepts in switching and routing, is familiar with IP routing, and understands basic switch architectures (for example shared memory, cross-bar, and multi-stage architectures), so that the workshop can focus primarily on the practical and theoretical details of the operation, performance, implementation, and limitations of these architectures.

Workshop Duration: Expected duration is 2 days (with 6 hours of instruction and Q A each).

Workshop Goals: To help the audience walk away with a detailed understanding of the operation of canonical high-speed switch architectures, an appreciation of some key trade-offs in the design of such switch cores, and an understanding of the architecture of the systems and networks where these switches fit. The attendees leave with an intuitive understanding of the concepts and technologies involved, and the ability to rapidly apply their learning to the development of software, chips, hardware and systems, or use this knowledge for making intelligent deployment decisions for carrier networks.

 

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